Andy Nightingale, VP of Product Advertising and marketing at Arteris is a seasoned world enterprise chief with a various background in engineering and product advertising. He’s a Chartered Member of the British Pc Society and the Chartered Institute of Advertising and marketing, and has over 35 years of expertise within the high-tech {industry}.
All through his profession, Andy has held a variety of roles, together with engineering and product administration positions at Arm, the place he spent 23 years. In his present function as VP of product advertising at Arteris, Andy oversees the Magillem system-on-chip deployment tooling and FlexNoC and Ncore network-on-chip merchandise.
Arteris is a catalyst for system-on-chip (SoC) innovation because the main supplier of semiconductor system IP for the acceleration of SoC growth. Arteris Community-on-Chip (NoC) interconnect mental property (IP) and SoC integration know-how allow greater product efficiency with decrease energy consumption and sooner time to market, delivering confirmed flexibility and higher economics for system and semiconductor firms, so progressive manufacturers are free to dream up what comes subsequent.
Along with your intensive expertise at Arm and now main product administration at Arteris, how has your perspective on the evolution of semiconductor IP and interconnect applied sciences modified through the years? What key traits excite you essentially the most in the present day?
It’s been a rare journey—from my early days writing check benches for ASICs at Arm to serving to form product technique at Arteris, the place we’re on the forefront of interconnect IP innovation. Again in 1999, system complexity quickly accelerated, however the focus was nonetheless totally on processor efficiency and important SoC integration. Verification methodologies have been evolving, however interconnect was typically seen as a hard and fast infrastructure—mandatory however not strategic.
Quick-forward to in the present day and interconnect IP has develop into a crucial enabler of SoC (System-on-Chip) scalability, energy effectivity, and AI/ML efficiency. The rise of chiplets, domain-specific accelerators, and multi-die architectures has positioned immense stress on interconnect applied sciences to develop into extra adaptive, progressive, bodily, and software-aware.
One of the crucial thrilling traits I see is the convergence of AI and interconnect design. At Arteris, we’re exploring how machine studying can optimize NoC (Community-on-Chip) topologies, intelligently route knowledge site visitors, and even anticipate congestion to enhance real-time efficiency. This isn’t nearly pace—it is about making programs extra progressive and responsive.
What excites me is how semiconductor IP is changing into extra accessible to AI innovators. With high-level SoC configuration IP and abstraction layers, startups in automotive, robotics, and edge AI can now leverage superior interconnect architectures with no need a deep background in RTL design. That democratization of functionality is gigantic.
One other key shift is the function of digital prototyping and system-level modeling. Having labored on ESL (Digital System Degree) instruments early in my profession, it’s rewarding to see these methodologies now enabling early AI workload analysis, efficiency prediction, and architectural trade-offs lengthy earlier than silicon is taped out.
Finally, the way forward for AI is determined by how effectively we transfer knowledge—not simply how briskly we course of it. That’s why I consider the evolution of interconnect IP is central to the subsequent era of clever programs.
Arteris’ FlexGen leverages AI pushed automation and machine studying to automate NoC (Community-on-Chip) topology era. How do you see AI’s function evolving in chip design over the subsequent 5 years?
AI is essentially reworking chip design, and over the subsequent 5 years, its function will solely deepen—from productiveness assist to clever design associate. At Arteris, we’re already dwelling that future with FlexGen, the place AI, formal strategies, and machine studying are central to automating Community-on-Chip (NoC) topology optimization and SoC integration workflows.
What units FlexGen aside is its mix of ML algorithms—all mixed to initialize floorplans from pictures, generate topologies, configure clocks, cut back Clock Area Crossings, and optimize the connectivity topology and its placement and routing bandwidth, streamlining communication between IP blocks. Furthermore, that is all carried out deterministically, that means that outcomes will be replicated and incremental changes made, enabling predictable best-in-class outcomes to be used circumstances starting from AI help for an professional SoC designer to creating the appropriate NoC for a novice.
Over the subsequent 5 years, AI’s function in chip design will shift from helping human designers to co-designing and co-optimizing with them—studying from each iteration, navigating design complexity in real-time, and finally accelerating the supply of AI-ready chips. We see AI not simply making chips sooner however making sooner chips smarter.
The semiconductor {industry} is witnessing fast innovation with AI, HPC, and multi-die architectures. What are the most important challenges that NoC design wants to resolve to maintain up with these developments?
As AI, HPC, and multi-die architectures drive unprecedented complexity, the most important problem for NoC design is scalability with out sacrificing energy, efficiency, or time to market. At present’s chips characteristic tens to lots of of IP blocks, every with totally different bandwidth, latency, and energy wants. Managing this variety—throughout a number of dies, voltage domains, and clock domains—requires NoC options that go far past guide strategies.
NoC resolution applied sciences similar to FlexGen assist deal with key bottlenecks: minimizing wire size, maximizing bandwidth, aligning with bodily constraints, and doing every thing with pace and repeatability.
The way forward for NoC should even be automation-first and AI-enabled, with instruments that may adapt to evolving floorplans, chipset-based architectures, and late-stage modifications with out requiring full rework. That is the one option to hold tempo with trendy SoCs’ huge design cycles and heterogeneous calls for and guarantee environment friendly, scalable connectivity on the coronary heart of next-gen semiconductors.
The AI chipset market is projected to develop considerably. How does Arteris place itself to assist the rising calls for of AI workloads, and what distinctive benefits does FlexGen provide on this area?
Arteris just isn’t solely uniquely positioned to assist the AI chiplet market however has been doing this already for years by delivering automated, scalable Community-on-Chip (NoC) IP options purpose-built for the calls for of AI workloads together with Generative AI and Massive Language Fashions (LLM) compute —supporting excessive bandwidth, low latency, and energy effectivity throughout more and more complicated architectures. FlexGen, as the most recent addition to the Arteris NoC IP lineup, will play an much more vital function in quickly creating optimum topologies finest fitted to totally different large-scale, heterogeneous SoCs.
FlexGen gives incremental design, partial completion mode, and superior pathfinding to dynamically optimize NoC configurations with out full redesigns—crucial for AI chips that evolve all through growth.
Our clients are already constructing Arteris know-how into multi-die and chiplet-based programs, effectively routing site visitors whereas respecting floorplan and clock area constraints on every chiplet. Non-coherent multi-die connectivity is supported over industry-standard interfaces offered by third- occasion controllers.
As AI chip complexity grows, so does the necessity for automation, adaptability, and pace. FlexGen delivers all three, serving to groups construct smarter interconnects—sooner—to allow them to give attention to what issues: advancing AI efficiency at scale.
With the rise of RISC-V and customized silicon for AI, how does Arteris’ method to NoC design differ from conventional interconnect architectures?
Conventional interconnect architectures have been primarily constructed for fixed-function designs, however in the present day’s RISC-V and customized AI silicon demand a extra configurable, scalable, and automatic method than a modified one-size-fits-all resolution. That’s the place Arteris stands aside. Our NoC IP, particularly with FlexGen, is designed to adapt to the variety and modularity of contemporary SoCs, together with customized cores, accelerators, and chiplets, as talked about above.
FlexGen permits designers to generate and optimize topologies that replicate distinctive workload traits, whether or not low-latency paths for AI inference or high-bandwidth routes for shared reminiscence throughout RISC-V clusters. In contrast to static interconnects, FlexGen’s algorithms tailor every NoC to the chip’s structure throughout clock domains, voltage islands, and floorplan constraints.
In consequence, Arteris permits groups constructing customized silicon to maneuver sooner, cut back danger, and get essentially the most from their extremely differentiated designs—one thing conventional interconnects weren’t constructed to deal with.
FlexGen claims a 10x enchancment in design iteration pace. Are you able to stroll us via how this automation reduces complexity and accelerates time-to-market for System-on-Chip (SoC) designers?
FlexGen delivers a 10x enchancment in design iteration pace by automating a number of the most complicated and time-consuming duties in NoC design. As an alternative of manually configuring topologies, resolving clock domains, or optimizing routes, designers use FlexGen’s bodily conscious, AI-powered engine to deal with these in hours (or much less)—duties that historically took weeks.
As talked about above, partial completion mode can robotically end even partially accomplished designs, preserving guide intent whereas accelerating timing closure.
The result’s a sooner, extra correct, and easier-to-iterate design stream, enabling SoC groups to discover extra architectural choices, reply to late-stage modifications, and get to market sooner—with higher-quality outcomes and fewer danger of expensive rework.
One in every of FlexGen’s standout options is wire size discount, which improves energy effectivity. How does this affect general chip efficiency, notably in power-sensitive purposes like edge AI and cellular computing?
Wire size instantly impacts energy consumption, latency, and general chip effectivity—each in cloud AI / HPC purposes that use the extra superior nodes and edge AI inference purposes the place each milliwatt issues. FlexGen’s means to robotically decrease wire size—typically as much as 30%—means shorter knowledge paths, diminished capacitance, and fewer dynamic energy draw.
In real-world phrases, this interprets to decrease warmth era, longer battery life, and higher performance-per-watt, all of that are crucial for AI workloads on the edge or in cellular environments and the cloud by instantly impacting the overall value of possession (TCO). By optimizing the NoC topology with AI-guided placement and routing, FlexGen ensures that efficiency targets are met with out sacrificing energy effectivity—making it an excellent match for in the present day and tomorrow’s energy-sensitive designs.
Arteris has partnered with main semiconductor firms in AI knowledge facilities, automotive, client, communications, and industrial electronics. Are you able to share insights on how FlexGen is being adopted throughout these industries?
Arteris NoC IP sees sturdy adoption throughout all markets, notably for high-end, extra superior chiplets and SoCs. That’s as a result of it addresses every sector’s prime challenges: efficiency, energy effectivity, and design complexity whereas preserving the core performance and space constraints.
In automotive, for instance, firms like Dream Chip use FlexGen to hurry up the intersection of AI and Security for autonomous driving by leveraging Arteris for his or her ADAS SoC design whereas assembly strict energy and security constraints. FlexGen’s good NoC optimization and era in knowledge facilities assist handle huge bandwidth calls for and scalability, particularly for AI coaching and general acceleration workloads.
FlexGen gives a quick, repeatable path to optimized NoC architectures for industrial electronics, the place design cycles are tight and product longevity is essential. Clients worth its incremental design stream, AI-based optimization, and talent to adapt rapidly to evolving necessities, making FlexGen a cornerstone for next-generation SoC growth.
The semiconductor provide chain has confronted vital disruptions lately. How is Arteris adapting its technique to make sure Community-on-Chip (NoC) options stay accessible and scalable regardless of these challenges?
Arteris responds to produce chain disruptions by doubling down on what makes our NoC options resilient and scalable: automation, flexibility, and ecosystem compatibility.
FlexGen helps clients design sooner and stay extra agile to regulate to altering silicon availability, node shifts, or packaging methods. Whether or not they’re doing spinoff designs or creating new interconnects from scratch.
We additionally assist clients with totally different course of nodes, IP distributors, and design environments, making certain clients can deploy Arteris options no matter their foundry, EDA instruments, or SoC structure.
By lowering dependency on anybody a part of the provision chain and enabling sooner, iterative design, we’re serving to clients derisk their designs and keep on schedule —even in unsure occasions.
Wanting forward, what are the most important shifts you anticipate in SoC growth, and the way is Arteris making ready for them?
One of the crucial vital shifts in SoC growth is the transfer towards heterogeneous architectures, chiplet-based designs, and AI-centric workloads. These traits demand way more versatile, scalable, and clever interconnects—one thing conventional strategies can’t sustain with.
Arteris is making ready by investing in AI-driven automation, as seen in FlexGen, and increasing assist for multi-die programs, complicated clock/energy domains, and late-stage floorplan modifications. We’re additionally targeted on enabling incremental design, sooner iteration, and seamless IP integration—so our clients can hold tempo with shrinking growth cycles and rising complexity.
Our purpose is to make sure SoC (and chiplet) groups keep agile, whether or not they’re constructing for edge AI, cloud AI, or something in between, all whereas offering the most effective energy, efficiency, and space (PPA) irrespective of the complexity of the design, XPU structure, and foundry node used.
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